Alif Semiconductor /AE302F80F5582AE_CM55_HE_View /SDMMC /SDMMC_EMBEDDED_CTRL_R

Number of Clock Pins (SD Mode). This field indicates support of clock pins to select one of devices for shared bus system. Up to 7 clock pins can be supported.

0 (Val_0x0): Shared bus not supported

1 (Val_0x1): 1 SD_CLK supported

2 (Val_0x2): 2 SD_CLK supported

7 (Val_0x7): 7 SD_CLK supported

Number of Interrupt Input Pins. This field indicates support of interrupt input pins for an embedded system.

Bus Width Preset (SD Mode). Each bit of this field specifies the bus width for each embedded device. The shared bus supports mixing of 4-bit and 8-bit bus width devices. Bit 8: Bus Width Preset for Device 1 Bit 9: Bus Width Preset for Device 2 Bit 10: Bus Width Preset for Device 3 Bit 11: Bus Width Preset for Device 4 Bit 12: Bus Width Preset for Device 5 Bit 13: Bus Width Preset for Device 6 Bit 14: Bus Width Preset for Device 7 Function of each bit is defined as follows:

0 (Val_0x0): 4-bit bus width mode

1 (Val_0x1): 8-bit bus width mode

Clock Pin Select (SD Mode). This bit is selected by one of clock pin outputs.

0 (Val_0x0): Clock pins are disabled

1 (Val_0x1): CLK[1] is selected

2 (Val_0x2): CLK[2] is selected

7 (Val_0x7): CLK[7] is selected

Interrupt Pin Select. These bits enable the interrupt pin inputs.

0 (Val_0b000): Interrupts (INT_A, INT_B, INT_C) are disabled

1 (Val_0b001): INT_A is enabled

2 (Val_0b010): INT_B is enabled

4 (Val_0b100): INT_C is enabled

Back-End Power Control (SD Mode). Each bit of this bit field controls back-end power supply for an embedded device. Bit 24: Back-End Power for Device 1 Bit 25: Back-End Power for Device 2 Bit 26: Back-End Power for Device 3 Bit 27: Back-End Power for Device 4 Bit 28: Back-End Power for Device 5 Bit 29: Back-End Power for Device 6 Bit 30: Back-End Power for Device 7 Function of each bit is defined as follows:

0 (Val_0x0): Back-End Power is off

1 (Val_0x1): Back-End Power is supplied